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| Rev. 1.0, Jan. 2010 K8P2716UZC 128Mb C-die Page NOR Flash 56Pin TSOP(20x14mm), 64ball FBGA (11x13, 1.0mm ball pitch) Page Mode, (8M x16, 16Mb x8) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2009 Samsung Electronics Co., Ltd. All rights reserved. -1- K8P2716UZC datasheet History - Initial draft - Ordering inforation revised - ICC6 is changed from Typ. 6mA and Max. 10mA to Typ. 10mA and Max. 15mA - CFI (Common Flash Memory Interface Code) of address 2Dh changed from 00FFh to 007Fh. - Specification finalized Rev. 1.0 NOR FLASH MEMORY Revision History Revision No. 0.0 0.1 Draft Date Jul. 06, 2009 Oct. 05, 2009 Remark Target Target Editor - 1.0 Jan. 08, 2010 Final - -2- K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY Table Of Contents 128Mb C-die Page NOR Flash 1.0 FEATURES................................................................................................................................................................. 5 2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5 3.0 PIN DESCRIPTION .................................................................................................................................................... 6 4.0 56TSOP PIN CONFIGURATION ................................................................................................................................ 7 5.0 64 Ball FBGA TOP VIEW (BALL DOWN) ................................................................................................................... 7 6.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 8 7.0 ORDERING INFORMATION ...................................................................................................................................... 9 8.0 PRODUCT INTRODUCTION...................................................................................................................................... 10 9.0 COMMAND DEFINITIONS ......................................................................................................................................... 11 10.0 DEVICE OPERATION .............................................................................................................................................. 16 10.1 Read Mode ............................................................................................................................................................ 16 10.2 Standby Mode ....................................................................................................................................................... 16 10.3 Output Disable....................................................................................................................................................... 16 10.4 Automatic Sleep Mode .......................................................................................................................................... 16 10.5 Autoselect Mode.................................................................................................................................................... 16 10.6 Write (Program/Erase) Mode................................................................................................................................. 17 10.6.1 Program .......................................................................................................................................................... 17 10.6.2 Writer Buffer Programming ............................................................................................................................. 18 10.6.3 Accelerated Program Operation...................................................................................................................... 19 10.6.4 Unlock Bypass ................................................................................................................................................ 20 10.6.5 Chip Erase ...................................................................................................................................................... 20 10.6.6 Block Erase ..................................................................................................................................................... 20 10.7 Erase Suspend / Resume...................................................................................................................................... 21 10.8 Program Suspend / Resume ................................................................................................................................. 21 10.9 Write Protect (WP)................................................................................................................................................. 22 10.10 Software Reset .................................................................................................................................................... 22 10.11 Hardware Reset................................................................................................................................................... 22 10.12 Power-up Protection ............................................................................................................................................ 23 10.13 Low Vcc Write Inhibit ........................................................................................................................................... 23 10.14 Write Pulse Glitch Protection............................................................................................................................... 23 10.15 Logical Inhibit....................................................................................................................................................... 23 11.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 24 12.0 OTP BLOCK REGION .............................................................................................................................................. 24 12.1 OTP Block Protection ............................................................................................................................................ 24 13.0 ENHANCED BLOCK PROTECTION / UNPROTECTION ........................................................................................ 25 13.1 Block Protection..................................................................................................................................................... 26 13.2 Persistent Protection Bits ...................................................................................................................................... 26 13.3 Dynamic Protection Bits ........................................................................................................................................ 27 13.4 Persistent Protection Bit Lock Bit .......................................................................................................................... 27 13.5 Password Protection Method................................................................................................................................. 27 13.6 Master locking bit set............................................................................................................................................. 27 14.0 DEVICE STATUS FLAGS......................................................................................................................................... 36 15.0 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 39 16.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )......................................................... 39 17.0 DC CHARACTERISTICS.......................................................................................................................................... 40 18.0 CAPACITANCE(TA = 25 C, VCC = 3.0V, f = 1.0MHz) ............................................................................................ 40 19.0 AC TEST CONDITION.............................................................................................................................................. 41 20.0 AC CHARACTERISTICS .......................................................................................................................................... 41 20.1 Read Operations ................................................................................................................................................... 41 20.2 Write(Erase/Program)Operations .......................................................................................................................... 44 -3- K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 21.0 ERASE AND PROGRAM PERFORMANCE............................................................................................................. 45 22.0 PACKAGE DIMENSIONS......................................................................................................................................... 55 22.1 56-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE .................................................................... 55 22.2 64-Ball Fine Ball Grid Array Package (measured in millimeters)........................................................................... 56 -4- K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 128M Bit (8M x16, 16Mb x8) Page Mode / Page NOR Flash Memory 1.0 FEATURES * Single Voltage, 2.7V to 3.6V for Read and Write operations * Organization 8M x16 bit (Word mode) 16M x 8 bit (Byte mode) * Fast Read Access Time : 65ns * Page Mode Operation 8 Words Page access allows fast asychronous read Page Read Access Time : 25ns * Uniform block architectures 64Kword x 128 (Uniform) * OTP Block : Extra 256 word - 128word for factory and 128word for customer OTP * Power Consumption (typical value) - Active Read Current : 30mA (@5MHz) - Program/Erase Current : 25mA - Standby Mode/Auto Sleep Mode : 20uA * Support Single & 32word Buffer Program * WP/ACC input pin - Allows special protection of first or last block of flash array at VIL, regardless of block protect status - Removes special protection at VIH, the first or last block of flash array return to normal block protect status - Reduce program time at VHH : 6us/word at Write Buffer * Erase Suspend/Resume * Program Suspend/Resume * Unlock Bypass Mode * Hardware RESET Pin * Command Register Operation * Supports Common Flash Memory Interface * Industrial Temperature : -40C to 85C * Extended Temperature : -25C to 85C * Endurance : 100Kcycle * VIO options at 1.8V and 3V I/O * Package options - 56 Pin TSOP (20x14mm) - 64 Ball FBGA (11x13, 1.0mm Ball Pitch) 2.0 GENERAL DESCRIPTION The K8P2716UZB featuring single 3.0V power supply, is an 128Mbit NORtype Flash Memory organized as 16M x 8 or 8M x16. The memory architecture of the device is designed to divide its memory arrays into 128 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The K8P2716UZB NOR Flash consists of uniform block. The K8P2716UZB offers fast page access time of 25ns with random access time of 65ns. The devices fast access times allow high speed microprocessors to operate without wait states. The device performs a program operation in unit of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 25mA as program/erase current in the commercial and extended temperature ranges. The K8P2716UZB NOR Flash Memory is created by using Samsung's advanced CMOS process technology. This device is available in 64FBGA and 56 Pin TSOP. The device is compatible with EPROM applications to require high-density and cost-effective nonvolatile read/write storage solutions. -5- K8P2716UZC datasheet Pin Name A0 - A22 Rev. 1.0 NOR FLASH MEMORY 3.0 PIN DESCRIPTION Pin Function Address Inputs Data Inputs / Outputs DQ15 - Data Inputs / Outputs in word mode A-1 - Address input in byte mode Chip Enable Output Enable Hardware Reset Pin Word/Byte selection Ready/Busy Output Write Enable Hardware Write Protection/Program Acceleration Power Supply Ground No Connection DQ0 - DQ14 DQ15/A-1 CE OE RESET BYTE RY/BY WE WP/ACC Vcc VSS NC -6- K8P2716UZC datasheet NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Rev. 1.0 NOR FLASH MEMORY NC NC A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 NC VIO 4.0 56TSOP PIN CONFIGURATION 56-pin TSOP1 Standard Type 14mm x 20mm 5.0 64 Ball FBGA TOP VIEW (BALL DOWN) A B C D E F G H 8 NC A22 NC Vio Vss NC NC NC 7 6 A13 A12 A14 A15 A16 BYTE DQ15/A-1 Vss A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 5 WE RESET A21 A19 DQ5 DQ12 Vcc DQ4 4 RY/BY WP/ACC A18 A20 DQ2 DQ10 DQ11 DQ3 3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 2 A3 A4 A2 A1 A0 CE OE Vss 1 NC NC NC NC NC Vio NC NC -7- K8P2716UZC datasheet Address Rev. 1.0 NOR FLASH MEMORY 6.0 FUNCTIONAL BLOCK DIAGRAM Vcc Vss CE OE WE RESET RY/BY BYTE WP/ACC A0(A-1)~A22 DQ0~DQ15 Block Inform Program Control Erase Control High Voltage Gen. I/O Interface X Dec Cell Array Latch & Control Y Dec -8- K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 7.0 ORDERING INFORMATION K8 P 27 16 U Z C - J I 4C Samsung NOR Flash Memory Access Time 4C : 65ns/25ns 4D : 70ns/30ns 4E : 80ns/30ns Operating Temperature Range C : Commercial Temp. (0 C to 70 C) E : Extended Temp. (-25 C to 85 C) I : Industrial Temp. (-40 C to 85 C) Package J : 64FBGA (Lead Free, Halogen Free, 1.0mm ball pitch) Q : 56TSOP1(Lead Free, Halogen Free) Version C : 4th Generation Block Architecture Z : Uniform Block Device Type P : Page Mode Density 27 : 128Mbits, Single Bank Organization 16 : x16 , x8 Organization Operating Voltage Range U : 2.7 V to 3.6V [Table 1] PRODUCT LINE-UP 4C Vcc VIO2) Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) Max. Page Access Time (ns) 2.7V~3.6V 2.7V~3.6V 65ns 65ns 25ns 25ns 4D 2.7V~3.6V 2.7V~3.6V 70ns 70ns 30ns 30ns 4E 2.7V~3.6V 1.7V~Vcc 80ns 80ns 30ns 30ns NOTE : 1) The device supports only 4E at VIO = 1.7~1.95V. 2) Contact samsung sales office for specification change points when low VIO option is required. [Table 2] K8P2716UZB DEVICE BLOCK DIVISIONS Mbit 128 Mbit Block Sizes 64 Kw x 128 [Table 3] OTP BLOCK Block Address A22~A8 OTP 0000h Area Factory-Locked Area Customer-Locked Area Block Size 128 words 128 words Address Range 000000h-00007Fh 000080h-0000FFh After entering OTP block, any issued addresses should be in the range of OTP block address -9- K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 8.0 PRODUCT INTRODUCTION The K8P2716UZB is 128Mbit NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 128 blocks (64 Kw x 128). Programming is done in units of 16 bits (Word) or 8 bits (Byte). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. The device offers fast page access time of 25ns with random access time of 65ns supporting high speed microprocessors to operate without any wait states. The command set of K8P2716UZB is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8P2716UZB is implemented with Internal Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8P2716UZB has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. [Table 4] Operations Table Operation CE OE WE WP/ACC A0(A-1) ~ A22 AIN X X X AIN DQ0 ~ DQ7 DQ8 ~ DQ15 BYTE = VIH DOUT High-Z High-Z High-Z DIN BYTE = VIL DQ8 ~ 14 = High-z DQ15 = A-1 High-Z High-Z High-Z DQ8 ~ 14 = High-z DQ15 = A-1 RESET Read Stand-by Output Disable Reset Write L Vcc0.3V L X L L X H X H H X H X L X H X X X (Note 1) DOUT High-Z High-Z High-Z DIN H Vcc0.3V H L H NOTE : L = VIL (Low), H = VIH (High), AIN = Address in, DIN = Data in, DOUT = Data out, X = Don't care. 1) WP/ACC must be VIH when writing on the outermost block. (BA0 or BA127) 2) Address for word mode is AMax:0. Address for byte mode is AMax:A-1. - 10 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 9.0 COMMAND DEFINITIONS The K8P2716UZB operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 5. [Table 5] Command Sequences (x16) Command Sequence Read Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Unlock Bypass Addr Data Unlock Bypass Program Addr Data Addr Data Addr Data Unlock Bypass Reset Addr Data Chip Erase Addr Data Addr Data Addr Data Addr Data 6 2 2 2 2 3 Cycle 1 1st Cycle RA RD XXXH F0H 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH BA 29H 555H AAH 555H AAH XXXH XXXH A0H XXXH XXXH 80H XXXH XXXH 80H XXXH XXXH 90H 555H AAH 555H AAH XXXH B0H XXXH 30H 2AAH 55H 2AAH 55H PA PD BA 30H XXXH 10H XXXH XXXH 00H 2AAH 55H 2AAH 55H 555H 80H 555H 80H 555H AAH 555H AAH 2AAH 55H 2AAH 55H 555H 10H BA 30H 555H F0H 555H 20H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 555H 90H 555H 90H 555H 90H 555H 90H 555H 90H 555H A0H BA 25H X00H ECH X01H 227EH BA / X02H (SeeTable6) X03H (See Table 6) X07H (See Table 6) PA PD BA WC WBL PD WBL PD X0EH 2266H X0FH 2260H 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Reset 1 Autoselect Manufacturer ID 1), 2) Autoselect Device ID1), 2), 3) Autoselect Block Protect Verify 1), 2) Autoselect Indicator Bit 1), 2) Autoselect Master Locking Bit 1), 2) Program 4 6 4 4 4 4 Write to Buffer 4) Program Buffer to Flash 6 1 Write to Buffer Abort Reset 4) 3 Unlock Bypass Block Erase Unlock Bypass Chip Erase Block Erase 6 Block Erase Suspend 5), 6) Block Erase Resume 1 1 - 11 - K8P2716UZC datasheet Command Definitions Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 1st Cycle XXXH B0H XXXH 30H X55H 98H 555H AAH 555H AAH RA RD 555H AAH 2AAH 55H 2AAH 55H 2AAH 55H 2nd Cycle Rev. 1.0 NOR FLASH MEMORY 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Program Suspend 7) ,8) Program Resume 1 CFI Query 9) Enter OTP Block Region 1 3 555H 88H 555H A0H PA PD OTP Block Program 4 OTP Block Read 1 Exit OTP Block Region 4 555H 90H XXXH 00H NOTE : * RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data, WBL : Write Buffer Location * BA : Block Address (A16 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . * DQ8 - DQ15 are don't care in command sequence, except for RD and PD * A14 - A22 are also don't care, except for the case of special notice. 1) To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 2) The 4th cycle data of Autoselect mode is output data. 3) Device ID must be read across cycles 4, 5 and 6. Device ID data : X0EH = "2266H", X0FH = "2260H" for 128Mb Uniform Block Device 4) Command sequence resets device for next command after write-to-buffer operation. 5) The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 6) The Erase Suspend command is applicable only to the Block Erase operation. 7) The Read Operation is allowed in the Program Suspend mode. 8) The Program Suspend command is applicable to Program and Erase Suspend - Program operation. 9) Command is valid when the device is in read mode or Autoselect mode. - 12 - K8P2716UZC datasheet Table 5 : Command Sequences (x8) Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 1 4 6 4 4 4 6 1 3 3 2 2 2 2 6 6 1 1 1st Cycle RA RD XXXH F0H AAAH AAH AAAH AAH AAAH AAH AAAH AAH AAAH AAH AAAH AAH BA 29H AAAH AAH AAAH AAH XXXH A0H XXXH 80H XXXH 80H XXXH 90H AAAH AAH AAAH AAH XXXH B0H XXXH 30H 555H 55H 555H 55H PA PD BA 30H XXXH 10H XXXH 00H 555H 55H 555H 55H AAAH 80H AAAH 80H 555H F0H AAAH 20H 555H 55H 555H 55H 555H 55H 555H 55H 555H 55H 555H 55H AAAH 90H AAAH 90H AAAH 90H AAAH 90H AAAH A0H BA 25H 2nd Cycle 3rd Cycle Rev. 1.0 NOR FLASH MEMORY 4th Cycle 5th Cycle 6th Cycle Command Sequence Read Reset Autoselect Manufacturer ID 1), 2) X00H ECH X02H XX7EH BA / X04H (See Table 6) X06H (See Table 6) PA PD BA WC WBL PD WBL PD X1CH XX66H X1EH XX60H Autoselect Device ID 1), 2), 3) Autoselect Block Protect Verify 1), 2) Autoselect Indicator Bit 1), 2) Program Write to Buffer 4) Program Buffer to Flash Write to Buffer Abort Reset 4) Unlock Bypass Unlock Bypass Program Unlock Bypass Block Erase Unlock Bypass Chip Erase Unlock Bypass Reset Chip Erase Block Erase Block Erase Suspend 5), 6) Block Erase Resume AAAH AAH AAAH AAH 555H 55H 555H 55H AAAH 10H BA 30H - 13 - K8P2716UZC datasheet Command Definitions Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 1 1 3 4 1 4 1st Cycle XXXH B0H XXXH 30H AAH 98H AAAH AAH AAAH AAH RA RD AAAH AAH 555H 55H 555H 55H 555H 55H 2nd Cycle Rev. 1.0 NOR FLASH MEMORY 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Program Suspend 7) ,8) Program Resume CFI Query 9) Enter OTP Block Region OTP Block Program OTP Block Read Exit OTP Block Region AAAH 88H AAAH A0H PA PD AAAH 90H XXXH 00H NOTE : * RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data, WBL : Write Buffer Location * BA : Block Address (A16 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . * DQ8 - DQ15 are don't care in command sequence, except for RD and PD * A14 - A22 are also don't care, except for the case of special notice. 1) To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 2) The 4th cycle data of Autoselect mode is output data. 3) Device ID must be read across cycles 4, 5 and 6. Device ID data : X0EH = "2266H", X0FH = "2260H" for 128Mb Top and Boot Block Device 4) Command sequence resets device for next command after write-to-buffer operation. 5) The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 6) The Erase Suspend command is applicable only to the Block Erase operation. 7) The Read Operation is allowed in the Program Suspend mode. 8) The Program Suspend command is applicable to Program and Erase Suspend - Program operation. 9) Command is valid when the device is in read mode or Autoselect mode. - 14 - K8P2716UZC [Table 6] K8P2716UZB Autoselect Codes datasheet CE OE WE A22 A16 A15 A10 A9 A8 ~ A7 X X X X X A6 A5 ~ A4 X X X X X A3 A2 A1 A0 Rev. 1.0 NOR FLASH MEMORY DQ15 - DQ8 BYT E= VIH X 22H 22H 22H X BYT E= VIL DQ7 - DQ0 Manufacturer ID Read Cycle1 Device ID Read Cycle2 Read Cycle3 Block Protection Verification L L L L L L L L L L H H H H H X X X X BA X X X X X VID VID VID VID VID L L L L L L L H H L L L H H L L L H H H L H L H L ECH 7EH 66H 60H 01H : (Protected : Either DYB or PPB locked) 99H : Factory Locked, Highest block conrolled by WP 19H : NOT Factory Locked, Highest block conrolled by WP 89H : Factory Locked, Lowest block conrolled by WP 09H : NOT Factory Locked, Lowest block conrolled by WP DQ7 : Factory Lock Bit 01H : Protected, 00H : Unprotected Indicator Bit(2) L L H X X VID X L X L L H H X Master locking bit Indicator Bit L L H BA X VID L L L L H H H X NOTE : 1) L=Logic Low=VIL, H=Logic High=VIH, VID = 8.5V to 9.5V, BA=Block Address, X=Don't care. Outermost block : BA127 or BA000 - 15 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 10.0 DEVICE OPERATION 10.1 Read Mode The K8P2716UZB is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CE or OE is high. The K8P2716UZB is available for 8-Word Page mode. Page mode provides fast access time for high performance system. After address access time(tAA), eight data words are loaded into an internal page buffer. A0 (A-1 in byte mode)~A2 bits determine which page word is output during a read operation. A3~A22 bits must be stable throughout the page read access. Figure 13 shows the asynchronous page read more timing. 10.2 Standby Mode The K8P2716UZB features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes. 10.3 Output Disable The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state. 10.4 Automatic Sleep Mode The K8P2716UZB features Automatic Sleep Mode to minimize the device power consumption. When addresses remain steady for tAA+30ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time. tAA + 30ns Address Outputs Data Data Data Data Auto Sleep Mode Data Data Figure 1: Auto Sleep Mode Operation 10.5 Autoselect Mode The K8P2716UZB offers the Autoselect Mode to identify manufacturer, device type and block protection verification by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The manufacturer, device code ,block protection verification and indicator bit can be read via the command register. The Command Sequence is shown in Table 6 and Figure 2. In addition, below Table 7 shows indicator bit in detail. The autoselect operation of block protection verification is initiated by first writing two unlock cycle. To terminate the autoselect operation, write Reset command (F0H) into the command register. Note : To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence can be written to an address within a device that is either in the read or erase-suspend-read mode. The Autoselect command cannot be written while the device is actively programming or erasing. Autoselect does not support page modes. The system must write the reset command to return to the read mode (or erase-suspend read mode if the device was previously in Erase Suspend). [Table 7] Indicator Bit Codes. Description DQ15 to DQ8 L DQ7 1=Factory-Locked 0=Not Locked DQ6 to DQ5 L DQ4 0 = WP Protects Block 255 1 = WP Protects Block 0 DQ3 DQ2 DQ1 DQ0 Indicator Bit H L L H - 16 - K8P2716UZC datasheet WE 2AAH Rev. 1.0 NOR FLASH MEMORY Address 555H 555H 00H 01H 0EH 0FH DQ15DQ0 AAH 55H 90H ECH 227EH 2266H 2260H Manufacturer ID NOTE : Please refer to Table 6 for device code. Device ID (K8P2716UZB) Figure 2: Autoselect Operation (by Command Sequence Method) 10.6 Write (Program/Erase) Mode The K8P2716UZB executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (whichever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard microprocessor write timing. 10.6.1 Program The K8P2716UZB can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. WE Address 555H 2AAH 555H Program Address A0H Program Data Program Start DQ15-DQ0 RY/BY AAH 55H Figure 3: Program Command Sequence - 17 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY In accross block boundaries and any sequence programming is allowed. A bit cannot be programmed from '0' back to '1'. If attempting to do, it may cause that device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still '0'. Only erase operations can convert a '0' to a '1'. 10.6.2 Writer Buffer Programming Write Buffer Programming allows the system write to a maximum of 32 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A22(max.) ~ A5 entered at fifth cycle. All subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A22(max.) ~ A5 as those entered at fifth cycle. Write buffer locations may be loaded in any order. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at the block address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 can be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. Note also that an address loaction cannot be loaded more than once into the write-buffer-page. WE Address DQ15-DQ0 RY/BY 555H 2AAH Block Address 55H 25H Block Address 12H WBL WBL Block Address 29H Program Start AAH PD PD Figure 4: Write Buffer Program Command Sequence The Write Buffer Programming Sequence can be aborted in the following ways: * Loading a value that is greater than the buffer size(32-word) during then number of word locations to Program step. (In case, WC > 1FH @Table6) * The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table 5) * Writing a Program address to have a different write-buffer-page with selected write-buffer-page ( Address bits A22(max) ~ A5 are different) * Writing non-exact "Program Buffer to Flash" command The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass mode. - 18 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 10.6.3 Accelerated Program Operation Accelerated program operation reduces the program time through the ACC function. This is one of two functions provided by the WP/ACC pin. When the WP/ACC pin is asserted as VHH, the device automatically enters the Unlock Bypass mode, and reduces the program operation time. Removing VHH from the WP/ACC pin returns the device to normal operation. Blocks must be unprotected before raising WP/ACC to VHH. Recommend that the WP/ACC pin must not be asserted at VHH except on accelerated program operation, or the device may be damaged. In addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Single word accelerated program operation The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-cycle (PA - PD) is for program address and data ). Accelerated Write Buffer Programming In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer to Flash" command sequence to be same as them of normal Write Buffer Programming and only can reduce the program time. Note that the third cycle of "Write to Buffer Abort Reset" command sequence is required in an Accelerated mode. When the WP/ACC pin is asserted as VHH, the device automatically enters the Unlock Bypass mode, and reduces the program operation time. Removing VHH from the WP/ACC pin returns the device to normal operation. * Program/Erase cycling must be limited below 100cycles for optimum performance. * Ambient temperature requirements : TA = 30C10C * The device automatically generates adequate program pulses and ignores other command after program command - 19 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 10.6.4 Unlock Bypass The K8P2716UZB provides the unlock bypass mode to save its operation time. This mode is possible for program, CFI, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence. Unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. The unlock bypass CFI command sequence is comprised of only one bus cycle; writing the unlock bypass program command (98H). This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. 10.6.5 Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. WE Address DQ15-DQ0 RY/BY 555H 2AAH 555H 555H 2AAH 555H 10H Chip Erase Start AAH 55H 80H AAH 55H Figure 5: Chip Erase Command Sequence 10.6.6 Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CE, while the Block Erase command is latched on the rising edge of WE or CE. Multiple blocks can be erased sequentially by writing the six bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command. - 20 - K8P2716UZC datasheet WE 555H 2AAH 555H 555H 2AAH Rev. 1.0 NOR FLASH MEMORY Address DQ15-DQ0 RY/BY Block Address 55H 30H Block Erase Start AAH 55H 80H AAH Figure 6: Block Erase Command Sequence 10.7 Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20us to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50us) , the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in don't care state. While erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. In the erase suspend mode, protect/unprotect command is prohibited. WE Address 555H Block Address AAH Block Erase Command Sequence 30H XXXH XXXH B0H DQ15-DQ0 30H Block Erase Start Erase Suspend Erase Resume Figure 7: Erase Suspend/Resume Command Sequence 10.8 Program Suspend / Resume The Program Suspend command interrupts the Program operation. Also the Program Suspend command interrupts the Program operation during Erase Suspend Mode. The Read operation is available only during Program Suspend. When the Program Suspend command is written during a Program operation, the device requires a maximum of 10us to suspend the Program operation. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. When the Program Resume command is executed, the Program operation will resume. When the Program Suspend or Program Resume command is executed, the addresses are in don't care state. While program can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. In the program suspend mode, protect/unprotect command is prohibited. - 21 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 10.9 Write Protect (WP) The WP/ACC pin has two useful functions. The one is that certain block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the outermost 64 Kword block (BA127 or BA0) on end of the flash array independently of whether that block was protected or unprotected. The write protected blocks can only be read. This is useful method to preserve an important program data. When the WP/ACC pin is asserted at VIH, the device reverts the outermost 64Kword block on an end to default protection state. Note that the WP/ACC pin must not be at VHH, for operations other than accelerated programming, or device damage may result. 10.10 Software Reset The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the device in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the device to read mode. If a device entered the autoselect mode in the Erase Suspend mode, the reset command returns the device to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the device to read mode or erase-suspend-read mode if the device was in the Erase Suspend state. 10.11 Hardware Reset The K8P2716UZB offers a reset feature by driving the RESET pin to VIL. When the RESET pin is held low(VIL) for at least a period of tRP, the device immediatley terminates any operation in progress, tristates all outputs, and ignores all read/write commands for duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. - 22 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 10.12 Power-up Protection To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. 10.13 Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 2.3V. 10.14 Write Pulse Glitch Protection Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle. 10.15 Logical Inhibit Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must be "0", while OE is "1". - 23 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 11.0 COMMON FLASH MEMORY INTERFACE Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode, the device enters the CFI mode. And then if the system writes the address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. 12.0 OTP BLOCK REGION The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. Indicator bit DQ7 are used to indicate the factory-locked of the part. The DQ7 is "1" for factory locked. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 5). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (000000h~0000FFh) normally and may check the Protection Verify Bit (DQ7) by using the "Autoselect Indicator Bit" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. 12.1 OTP Block Protection In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Locking operation to the OTP Block is started by writing the "Enter OTP Block Lock Register Region" Command sequence, and then the "OTP Block Lock Register Bit Program" Command sqeunce (Table 5) with data that have zero(setting to 0) in DQ0. Note that the other DQs except DQ0 will be ignored. The Locking operation has to be above 100us. After that timing, "Exit OTP Block Lock Register Region" command sequence or Hardware reset must be issued in order to exit OTP block mode and revert the device to read mode in main array. * The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. * Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operation. - 24 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 13.0 ENHANCED BLOCK PROTECTION / UNPROTECTION The Enhanced Block Protection / Unprotection feature disables or enables programming or erase operations in any or all blocks and can be implemented through software and/or hardware methods, which are independent of each other. Hardware Methods Software Methods Lock Register (One Time Programmable) #WP = ViL (Highest or lowest block locked) Password Method Persistent Method (DQ2) (DQ1) 64-bit Password (One Time Protect) PPB Lock Bit (Notes 1,2,3) 0 = PPBs Locked 1 = PPBs Unlocked Memory Array Block 0 Block 1 Block 2 Persistent Protection Bit (PPB) (Note 5,6) PPB 0 PPB 1 PPB 2 Dynamic Protection Bit (DYB) (Note 7,8,9) DYB 0 DYB 1 DYB 2 Block N-2 Block N-1 Block N (Note 4) PPB N-2 PPB N-1 PPB N DYB N-2 DYB N-1 DYB N Notes: 1. Bit is volatile, and defaults to 1 on reset. 2. Programming to 0 locks all PPBs to their current state. 3. Once programmed to 0, requires hardware reset to unlock. 4. N = Highest Address Block. 5. 0 = Sector Protected,1 = Sector Unprotected. 6. PPBs programmed individually, but cleared collectively. 7. 0 = Sector Protected,1 = Sector Unprotected. 8. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is 1 (unprotected). 9. Volatile Bits: defaults to user choice upon power-up (see ordering options). Figure 8: Enhanced Block Protection / Unprotection - 25 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 13.1 Block Protection Lock Register As shipped from the factory, all devices default to the persistent mode when power is applied, and all blocks are unprotected. (DYB is default to clear status : unprotected) For DYB set (protected status) in default, contact your local sales office for details. The device programmer or host system must then choose which block protection method to use. Programming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: - Lock Register Persistent Protection Mode Lock Bit (DQ1) - Lock Register Password Protection Mode Lock Bit (DQ2) [Table 8] Lock Register. Device DQ15 to DQ3 PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 K8P2716UZB Don't Care OTP Block Protection Bit NOTE : 1) If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2) After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Block 0 are disabled, while reads from other blocks are allowed until exiting this mode. 3) If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4) Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a block protection method, each block can operate in any of the following three states: 1. Constantly locked. The selected blocks are protected and cannot be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. 2. Dynamically locked. The selected blocks are protected and can be altered via software commands. 3. Unlocked. The blocks are unprotected and can be erased and/or programmed. 13.2 Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile for each block and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. NOTE : 1) Each PPB is individually programmed and all are erased in parallel. 2) Entry command disables reads and writes for the block selected. 3) Reads within that block 0 return the PPB status for that block. 4) Read and Write from other blocks than block 0 are allowed. 5) All Reads must be performed using the Asynchronous mode. 6) The specific block addresses (A22~A16) are written at the same time as the program command. 7) If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB. 8) There are no means for individually erasing a specific PPB and no specific block address is required for this operation. 9) Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for block 0. 10) The programming state of the PPB for a given block can be verified by writing a PPB Status Read Command to the device as described by the flow chart Below. - 26 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 13.3 Dynamic Protection Bits Dynamic Protection Bits are volatile and unique for each block and can be individually modified. DYBs only control the protection scheme for unprotected blocks that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each block in the protected or unprotected state respectively. This feature allows software to easily protect blocks against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. NOTE : 1) The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset, the DYBs is cleared. For DYB set (protected status) in default, contact your local sales office for details. 2) If the option to clear the DYBs after power up is chosen, (erased to 1), then the blocks maybe modified depending upon the PPB state of that block. 3) The blocks would be in the protected state If the option to set the DYBs after power up is chosen (programmed to 0). 4) It is possible to have blocks that are persistently locked with blocks that are left in the dynamic state. 5) The DYB Set or Clear commands for the dynamic blocks signify protected or unprotected state of the blocks respectively. However, if there is a need to change the status of the persistently locked blocks, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 6) To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when WP/ACC = VHH as they do when WP/ACC = VIH. 13.4 Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all blocks. When set (programmed to 0), this bit locks all PPB and when cleared (programmed to 1), unlocks each block. There is only one PPB Lock Bit per device. NOTE : 1) No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2) The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings. 13.5 Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent block Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for block PPBs modifications. NOTE : 1) There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set to prevent access. 2) The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. 3) The password is all 1s when shipped from the factory. 4) All 64-bit password combinations are valid as a password. 5) There is no means to verify what the password is after it is set. 6) The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7) The Password Mode Lock Bit is not erasable. 8) The lower two address bits (A1~ A0(A-1 in byte mode)) are valid during the Password Read, Password Program, and Password Unlock. 9) The exact password must be entered in order for the unlocking function to occur. 10) The Password Unlock command cannot be issued any faster than 1us at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11) Approximately 1us is required for unlocking the device after the valid 64-bit password is given to the device. 12) Password verification is only allowed during the password programming operation. 13) All further commands to the password region are disabled and all operations are ignored. 14) If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15) Entry command sequence must be issued prior to any of any operation and it disables reads and writes for block 0. Reads and writes for other blocks excluding block 0 are allowed. 16) If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. 17) A program or erase command to a protected block enables status polling and returns to read mode without having modified the contents of the protected block. 18) The programming of the DYB, PPB, and PPB Lock for a given block can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. 13.6 Master locking bit set This Master locking bit can ensure that protected blocks be permanently unalterable. Master locking bit is non-volatile bit. Master locking bit controls protection status of entire blocks that is protected by PPB. To make permanent protection block, PPB should be protected first. The usage of the master locking bit command sequence is absolutely required to ensure full protection of data from future alterations. If master locking bit is set ("0"), entire blocks that were protected by PPB are permanently protected. They are not changed and altered by any future lock/unlock commands. Anyone who uses this fuction needs much attention. Because there is no way to return to unlock status. Default status of master locking bit is unlock status("1"). If Master locking bit sets on unprotected block, the block still are remaining in status of unprotected block. Additionally the unprotected block can be protected by PPB program command. And then the block is protected permanently. - 27 - K8P2716UZC datasheet Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Rev. 1.0 NOR FLASH MEMORY Write Enter Lock Register Command: Address 555h, Data 40h XXXh = Address don't care Program Lock Register Data Address XXXh, Data A0h Address 00h, Data PD Program Data (PD): See text for Lock Register definitions Caution: Lock data may only be progammed once. Wait 4us Perform Polling Algorithm (see Write Operation Status flowchart) Yes Done? No DQ5=1? Yes No Error condition (Exceeded Timing Limits) PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. FAIL. Write rest command to return to reading array. Figure 9: Lock Register Program Algorithm - 28 - K8P2716UZC [Table 9] Block Protection examples Unique Device PPB Lock Bit 0 = locked, 1 = unlocked Any Block Any Block Any Block Any Block Any Block Any Block Any Block Any Block 0 0 0 0 1 1 1 1 Block PPB 0 = protected 0 0 1 1 0 0 1 1 datasheet Block DYB 0 = protected X X 1 0 X X 0 1 Rev. 1.0 NOR FLASH MEMORY Block Protection Status Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected - 29 - K8P2716UZC [Table 10] Block protection commands (x16) Command Definitions Enter Lock Register Region 25) Lock Register Bit Read Lock Register Bit Program 26) Exit Lock Register Region 27) Password Protection Command Set Entry 25) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Password Program Data Password Read Password Unlock Password Protection Command Set Exit 27) PPB Block Protection Command Set Entry 25) PPB Program All PPB Erase 22) PPB Status Read PPB Block Protection Command Set Exit 27) PPB Lock Bit Command Set Entry 25) PPB Lock Bit Set PPB Lock Bit Status Read PPB Lock Bit Command Set Exit 27) DYB Command Set Entry 25) DYB Set DYB Clear DYB Status Read DYB Command Set Exit 28) Master Locking Bit Set Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 4 7 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2 3 2 Cycle 3 1 2 2 3 datasheet 1st Cycle 555H AAH 00H RD XXXH A0H XXXH 90H 555H AAH XXXH A0H 00H PWD0 00H 25H XXXH 90H 555H AAH XXXH A0H XXXH 80H BA RD(0) XXXH 90H 555H AAH XXXH A0H XXXH RD(0) XXXH 90H 555H AAH XXXH A0H XXXH A0H BA RD(0) XXXH 90H 555H AAH XXXH 00H 2AAH 55H 555H F1H XXXH 00H 2AAH 55H BA 00H BA 01H 555H E0H XXXH 00H 2AAH 55H XXXH 00H 555H 50H XXXH DATA XXXH 00H 2AAH 55H PWA0/ PWA1/ PWA2/ PWD0/ PWD1 /PWD2/ 01H PWD1 00H 03H XXXH 00H 2AAH 55H BA 00H 00H 30H 555H C0H 555H 60H 2nd Cycle 2AAH 55H 3rd Cycle 555H 40H Rev. 1.0 NOR FLASH MEMORY 4th Cycle 5th Cycle 6th Cycle 7th Cycle 02H PWD2 00H PWD0 03H PWD3 01H PWD1 02H PWD2 03H PWD3 00H 29H - 30 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY NOTE : * RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data, WBL : Write Buffer Location * BA : Block Address (A16 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . * DQ8 - DQ15 are don't care in command sequence, except for RD and PD * A14 - A22 are also don't care, except for the case of special notice. * WC = Word Count. Number of write buffer locations to load minus 1. * PWA3 ~ PWA0 = Password Address. PWD3 ~ PWD0 = Password Data. PD3 ~ PD0 present four 16 bit combinations that represent the 64-bit Password * RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. 1) See bus operations description 2) All values are in hexadecimal. 3) Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, and password verify commands, and any cycle reading at RD(0) and RD(1). 4) Data bits DQ15 ~ DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 ~ PWD0. 5) Unless otherwise noted, these address bits are don't cares: (A22 ~ A14) 6) Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7) No unlock or command cycles required when reading array data. 8) The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when the deviceis in the autoselect mode, or if DQ5 goes high (while the device is providing status information) or performing block lock/unlock. 9) The fourth cycle of the autoselect command sequence is a read cycle. See Autoselect. 10) The data is 0000h for an unlocked block and 0001h for a locked block. 11) Device ID data : X0EH = "2266H", X0FH = "2260H" for 128Mb Uniform Block Device 12) See Autoselect. 13) The Unlock Bypass command sequence is required prior to this command sequence. 14) The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.The system may read and program in nonerasing blocks, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a block erase operation. 15) The Erase Resume command is valid only during the Erase Suspend mode. 16) Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 17) The entire four bus-cycle sequence must be entered for which portion of the password. 18) The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.The system may read and program in nonerasing blocks, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a block erase operation. 19) The Erase Resume command is valid only during the Erase Suspend mode. 20) Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 21) The entire four bus-cycle sequence must be entered for which portion of the password. 22) The ALL PPB ERASE command pre-programs all PPBs before erasure to prevent over-erasure of PPBs. 23) WP/ACC must be at VHH during the entire operation of this command. 24) Command sequence resets device for next command after write-to-buffer operation. 25) Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26) If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation aborts and returns the device to the default Persistent block Protection Mode. 27) The Exit command must be issued to reset the Block 0 of device into read mode. Otherwise the device hangs. 28) The Exit command must be issued to reset device into read mode. Otherwise the device hangs. - 31 - K8P2716UZC [Table 11] Block protection commands (x8) Command Definitions Enter Lock Register Region 25) Lock Register Bit Read Lock Register Bit Program 26) Exit Lock Register Region 27) Password Protection Command Set Entry 25) Password Program Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Password Read Data Addr Data Addr Password Unlock Data Addr Data Password Protection Command Set Exit 27) PPB Block Protection Command Set Entry 25) PPB Program All PPB Erase 22) PPB Status Read PPB Block Protection Command Set Exit 27) PPB Lock Bit Command Set Entry 25) PPB Lock Bit Set PPB Lock Bit Status Read PPB Lock Bit Command Set Exit 27) DYB Command Set Entry 25) DYB Set DYB Clear DYB Status Read DYB Command Set Exit 28) Master Locking Bit Set Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2 3 11 8 Cycle 3 1 2 2 3 2 datasheet 1st Cycle AAAH AAH 00H RD XXXH A0H XXXH 90H AAAH AAH XXXH A0H 00H PWD0 07H PWD7 00H 25H 05H PWD5 XXXH 90H AAAH AAH XXXH A0H XXXH 80H BA RD(0) XXXH 90H AAAH AAH XXXH A0H XXXH RD(0) XXXH 90H AAAH AAH XXXH A0H XXXH A0H BA RD(0) XXXH 90H AAAH AAH XXXH 00H 555H 55H AAAH F1H XXXH 00H 555H 55H BA 00H BA 01H AAAH E0H XXXH 00H 555H 55H XXXH 00H AAAH 50H 00H 03H 06H PWD6 XXXH 00H 555H 55H BA 00H 00H 30H AAAH C0H 00H PWD0 07H PWD7 XXXH DATA XXXH 00H 555H 55H PWAx PWDx 01H PWD1 02H PWD2 AAAH 60H 2nd Cycle 555H 55H 3rd Cycle AAAH 40H Rev. 1.0 NOR FLASH MEMORY 4th Cycle 5th Cycle 6th Cycle 7th Cycle 03H PWD3 04H PWD4 05H PWD5 06H PWD6 01H PWD1 00H 29 02H PWD2 03H PWD3 04H PWD4 - 32 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY NOTE : * RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data, WBL : Write Buffer Location * BA : Block Address (A16 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . * DQ8 - DQ15 are don't care in command sequence, except for RD and PD * A14 - A22 are also don't care, except for the case of special notice. * WC = Word Count. Number of write buffer locations to load minus 1. * PWA3 ~ PWA0 = Password Address. PWD7 ~ PWD0 = Password Word0, Word1, Word2, Word3 PD3 ~ PD0 present four 16 bit combinations that represent the 64-bit Password * RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. 1) See bus operations description 2) All values are in hexadecimal. 3) Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, and password verify commands, and any cycle reading at RD(0) and RD(1). 4) Data bits DQ15 ~ DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 ~ PWD0. 5) Unless otherwise noted, these address bits are don't cares: (A22 ~ A14) 6) Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7) No unlock or command cycles required when reading array data. 8) The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information) or performing block lock/unlock. 9) The fourth cycle of the autoselect command sequence is a read cycle. See Autoselect. 10) The data is 0000h for an unlocked block and 0001h for a locked block. 11) Device ID data : X0EH = "2266H", X0FH = "2260H" for 128Mb Uniform Block Device 12) See Autoselect. 13) The Unlock Bypass command sequence is required prior to this command sequence. 14) The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.The system may read and program in nonerasing blocks, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a block erase operation. 15) The Erase Resume command is valid only during the Erase Suspend mode. 16) Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 17) The entire four bus-cycle sequence must be entered for which portion of the password. 18) The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.The system may read and program in nonerasing blocks, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a block erase operation. 19) The Erase Resume command is valid only during the Erase Suspend mode. 20) Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 21) The entire four bus-cycle sequence must be entered for which portion of the password. 22) The ALL PPB ERASE command pre-programs all PPBs before erasure to prevent over-erasure of PPBs. 23) WP/ACC must be at VHH during the entire operation of this command. 24) Command sequence resets device for next command after write-to-buffer operation. 25) Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26) If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation aborts and returns the device to the default Persistent block Protection Mode. 27) The Exit command must be issued to reset the Block 0 of device into read mode. Otherwise the device hangs. 28) The Exit command must be issued to reset device into read mode. Otherwise the device hangs. - 33 - K8P2716UZC [Table 12] Common Flash Memory Interface Code Description datasheet 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH Rev. 1.0 NOR FLASH MEMORY Addresses (Byte Mode) 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H 0036H 0000H 0000H 0006H 0006H 0009H 0013H 0003H 0005H 0003H 0002H 0018H 0002H 0000H 0006H 0000H 0001H 007FH 0000H 0000H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Addresses (Word Mode) Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp Min. voltage(00H = no Vpp pin present) Vpp Max. voltage(00H = no Vpp pin present) Typical timeout per single word write 2 us N Typical timeout for Min. size buffer write 2 us(00H = not supported) N Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2 ms(00H = not supported) N Max. timeout for word write 2N times typical Max. timeout for buffer write 2 times typical N Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical(00H = not supported) Device Size = 2 byte N Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information - 34 - K8P2716UZC datasheet Description 40H 41H 42H 43H 44H 45H Rev. 1.0 NOR FLASH MEMORY Addresses (Byte Mode) 80H 82H 84H 86H 88H 8AH Data 0050H 0052H 0049H 0031H 0033H 0014H Addresses (Word Mode) Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 00 = Not Supported, 01 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme, 08 = Enhanced Block Protection Simultaneous Operation 00 = Not Supported, XX = Number of Blocks except Bank 0 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV WP protect 04 = Uniform Blocks Bottom WP protect. 05 = Uniform Blocks Top WP protect. Program Suspend 00 = Not Supported. 01 = Supported. 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 0002H 0001H 0000H 0008H 0000H 0000H 0002H 0085H 0095H 4FH 9EH 00XXH 50H A0H 0001H - 35 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 14.0 DEVICE STATUS FLAGS The K8P2716UZB has means to indicate its status of operation in the device where a program or erase operation is in processes. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3, DQ2 and DQ1. The statues are as follows : [Table 13] Hardware Sequence Flags Status Programming Block Erase or Chip Erase Erase Suspend Read Erase Suspend Read In Progress Erase Suspend Program Program Suspend Read Program Suspend Read Write to Buffer2) Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non-Program Suspended Block DQ7 DQ7 0 1 Data DQ7 Invalid Data DQ7 DQ7 DQ6 Toggle Toggle 1 Data Toggle Invalid Data Toggle Toggle DQ5 0 0 0 Data 0 Invalid Data 0 0 DQ3 0 1 0 Data 0 Invalid Data 0 0 DQ2 1 Toggle Toggle 1) Data 1 Invalid Data No Toggle No Toggle DQ1 0 1 1 Data 0 Invalid Data 0 1 BUSY State ABORT State NOTE : 1) DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) Note that DQ7 during Write-to-Buffer-Programming indicates the data-bar for DQ7 for the last loaded write-buffer address location. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. DQ6 : Toggle Bit Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. - 36 - K8P2716UZC DQ5 : Exceed Timing Limits datasheet Rev. 1.0 NOR FLASH MEMORY If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. DQ1 : Buffer Program Abort Indicator DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-toBuffer-Abort-Reset command sequence to return the device to reading array data. RY/BY : Ready/Busy The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor by system is required for proper operation. The K8P2716UZB has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the K8P2716UZB is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. Rp VCC Rp = Ready / Busy open drain output Vcc (Max.) - VOL (Max.) 3.5 V = 2.1mA + IL IOL + IL where IL is the sum of the input currents of all devices tied to the Ready / Busy pin. GND Device - 37 - K8P2716UZC datasheet Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address Rev. 1.0 NOR FLASH MEMORY DQ7 = Data ? No No Yes DQ6 = Toggle ? Yes No No DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 10: Data Polling Algorithms Figure 11: Toggle Bit Alogorithms - 38 - K8P2716UZC datasheet Parameter Vcc VIO WP/ACC and A9 All Other Pins Commercial Extended Symbol Vcc VIO 4) Rev. 1.0 NOR FLASH MEMORY 15.0 ABSOLUTE MAXIMUM RATINGS Rating -0.5 to +4.0 -0.5 to +4.0 -0.5 to +9.5 -0.5 to Vcc+0.5 -10 to +125 -25 to +125 -65 to +150 5 -40 to +85 -25 to + 85 C C mA C C V Unit Voltage on any pin relative to VSS VIN Tbias Tstg IOS TA (Industrial Temp.) TA (Extended Temp.) Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature NOTE : 1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2) Minimum DC voltage is -0.5V on WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on WP/ACC pins is 9.5V which, during transitions, may overshoot to 10.5V for periods <20ns. 3) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4) Contact samsung sales office for specification change points when low VIO option is required. 16.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) Parameter Supply Voltage VIO Supply Voltage Supply Voltage Symbol VCC VIO1) VSS Min 2.7 1.65 0 Typ. 3.0 0 Max 3.6 VCC 0 Unit V V V NOTE : 1) Contact samsung sales office for specification change points when low VIO option is required. - 39 - K8P2716UZC datasheet Symbol ILI ILIT ILO Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax, A9=9.5V VOUT=VSS to VCC,VCC=VCCmax Rev. 1.0 NOR FLASH MEMORY 17.0 DC CHARACTERISTICS Parameter Input Leakage Current A9 Input Leakage Current Output Leakage Current Vcc Active Read Current 1) VIO Non-Active Output 5) Active Write Current 2) Program While Erase Suspend Current Page Read Current ACC Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode Input Low Level Input High Level Voltage for Program Acceleration 4) Min - 1.0 - 1.0 TBD TBD Typ - Max + 1.0 35 + 1.0 TBD TBD Unit A A A TBD TBD mA mA mA mA A A A V V V V V V V ICC2 ICC5 ICC6 IACC ISB1 ISB2 ISB3 VIL VIH VHH VID VOL VOH VLKO CE=VIL, OE=VIH, WE=VIL CE=VIL, OE=VIH OE=VIH, 8-word Page Read CE=VIL, OE=VIH CE, RESET, WP/ACC= Vcc 0.3 RESET= Vss 0.3 VIH=Vcc 0.3V, VIL=VSS 0.2V Vcc=2.7~3.6V Vcc=2.7~3.6V Vcc = 2.7~3.6V Vcc = 2.7~3.6V IOL =100uA,Vcc=VCCmin IOH = -100uA, Vcc=VCCmin 40MHz -0.5 Vccx0.7 8.5 8.5 Vcc - 0.2 2.3 25 27 10 15 20 20 20 - 50 55 15 30 40 40 40 0.8 Vcc+0.3 9.5 9.5 0.1 2.5 Voltage for Autoselect and Temporary Sector Unprotect Output Low Level Output High Level Low VCC Lock-out Voltage NOTE : 1) The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). 2) ICC active during Internal Routine(program or erase) is in progress.. 3) The high voltage (VHH) must be used in the range of Vcc = 2.7V ~ 3.6V 4.)Not 100% tested. 5) Contact samsung sales office for specification change points when low VIO option is required. 18.0 CAPACITANCE(TA = 25 C, VCC = 3.0V, f = 1.0MHz) Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 10 10 10 Unit pF pF pF NOTE : Capacitance is periodically sampled and not 100% tested. - 40 - K8P2716UZC datasheet Parameter Input Pulse Levels Rev. 1.0 NOR FLASH MEMORY 19.0 AC TEST CONDITION Value 0V to Vcc 5ns Vcc/2 CL = 30pF Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc Vcc/2 0V Input & Output Test Point Device Vcc/2 CL * CL= 30pF including Scope and Jig Capacitance Input Pulse and Test Point Output Load 20.0 AC CHARACTERISTICS 20.1 Read Operations VCC = 2.7V~3.6V Parameter 1) Symbol Min 4C Max 65 65 25 25 16 Min 70 30 5 4D Max 70 70 30 30 16 Min 80 30 5 4E Max 80 80 30 30 16 - Unit Read Cycle Time tRC tPRC tAA tCE tOE tPA tDF tOH 65 25 5 ns ns ns ns ns ns ns ns Page Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time Page Address Access Time CE & OE Disable Time1) Output Hold Time from Address, CE or OE 1) NOTE : 1) Not 100% tested. The device supports only 4E at VIO = 1.7~1.95V. - 41 - K8P2716UZC datasheet tRC Rev. 1.0 NOR FLASH MEMORY SWITCHING WAVEFORMS Conventional Read Operations Address tAA Address Stable CE tOE tDF OE tOEH1 WE tCE tOH Outputs HIGH-Z Output Valid HIGH-Z RY/BY HIGH Figure 12: Conventional Read Operation Timings Page Read Operations A3 to A22 Same page Addresses A0(A-1): A2 Aa tRC tAA Ab tPRC Ac Ad Ae Af Ag Ah CE tCE OE tOEH1 tOE tDF WE tPA tOH High-Z tPA tOH tOH Output Da Db Dc Dd De Df Dg Dh Figure 13: Page Read Operation Timings - 42 - K8P2716UZC SWITCHING WAVEFORMS Hardware Reset/Read Operations RY/BY 0V datasheet tRC Rev. 1.0 NOR FLASH MEMORY Address tAA Address Stable CE tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid Figure 14: Hardware Reset/Read Operation Timings Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address, CE or OE RY/BY Recovery Time RESET Low to Standby Mode RESET Pulse Width RESET High Time Before Read Symbol tRC tAA tCE tOH tRB tRPD tRP tRH 4C Min 65 5 0 20 30 200 Max 65 65 Min 70 5 0 20 30 200 4D Max 70 70 Min 80 5 0 20 30 200 4E Max 80 80 - Unit ns ns ns ns ns s s ns NOTE : 1) The device supports only 4E at VIO = 1.7~1.95V. - 43 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY AC CHARACTERISTICS 20.2 Write(Erase/Program)Operations VCC = 2.7V ~ 3.6V Parameter Write Cycle Time 1), 3) Address Setup Time Address Setup Time to OE low during toggle bit polling Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time 1) Output Enable Hold Time CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Programming Operation 2) 2) Symbol Min tWC tAS tASO tAH tAHT tDS tDH tOES tOEH1 tOEH2 tCS tCH tWP tWPH tPGM tACCPGM tBERS tVCS tVHH tVPS tRB tBUSY tGHWL tCEPH tOEPH tBEA tESL tPSL tASP tPSP 250 250 1 0 0 20 10 65 0 15 35 0 30 0 0 0 10 0 0 35 25 All speed Max - Unit ns ns ns 6 (typ.) 6 (typ.) 0.7(typ) 90 50 20 10 100(typ) 1(typ) ns ns ns ns ns ns ns ns ns ns ns s s sec s ns us ns ns ns ns ns us us us us us Read 1) Toggle and Data Polling 1) Accelerated Programming Operation Block Erase Operation VCC Set Up Time VHH Set Up Time 2) ACC Setup Time (During Accelerated Programming) Write Recovery Time from RY/BY Program/Erase Valid to RY/BY Delay Read Recovery Time Before Write CE High during toggling bit polling OE High during toggling bit polling Block Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Block Protection Toggle Time During Programming Within a Protected Block NOTE : 1) Not 100% tested. 2) The duration of the Program or Erase operation varies and is calculated in the internal algorithms. 3) tWC : 65ns(min) : 4C option, 70ns(min) : 4D option, 80ns(min) : 4E option - 44 - K8P2716UZC datasheet Condition 64 Kword VCC VCC VCC ACC VCC ACC VCC ACC VCC Limits Min Typ 0.7 89.6 6 6 3 3 96 96 26 100 100 30 30 960 960 260 Max 3.5 Unit sec sec s s s sec Rev. 1.0 NOR FLASH MEMORY 21.0 ERASE AND PROGRAM PERFORMANCE Parameter Block Erase Time Chip Erase Time Word Programming Time Word Programming time with 32words Buffer Total 32-words Buffer Programming Time Chip Programming Time with 32word Buffer Comments Includes 00H programming prior to erasure Includes 00H programming prior to erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead NOTE : 1) 25 C, VCC = 3.0V 100,000 cycles, Typical (Checkerboard pattern), All values are subject to change. 2) System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure. - 45 - K8P2716UZC SWITCHING WAVEFORMS Program Operations tAS datasheet Data Polling PA tAH PA 555H Rev. 1.0 NOR FLASH MEMORY Address tRC CE OE tWP tWC tCH tPGM WE tCS tWPH tDH tOE tDF DATA RY/BY A0H tDS PD tBUSY Status DOUT tRB tCE tOH NOTE : 1) DQ7 is the output of the complement of the data written to the device. 2) DOUT is the output of the data written to the device. 3) PA : Program Address, PD : Program Data 4) The illustration shows the last two cycles of the program command sequence. Figure 15: Program Operation Timings VHH WP/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 16: Accelerated Program Timings - 46 - K8P2716UZC SWITCHING WAVEFORMS Chip/Block Erase Operations tAS datasheet 555H 2AAH tAH Rev. 1.0 NOR FLASH MEMORY 555H for Chip Erase 555H 555H 2AAH BA tRC Address CE Vih OE tWP tWC WE tCS tWPH tDH 10H for Chip Erase 55H 80H AAH 55H 30H DATA RY/BY AAH tDS Vcc tVCS Figure 17: Chip/Block Erase Operation Timings NOTE : 1) BA : Block Address - 47 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY SWITCHING WAVEFORMS Data Polling During Internal Routine Operation CE tOE tDF OE tOEH2 WE tCE tOH DQ7 Data In tPGM or tBERS DQ7 *DQ7 = Valid Data HIGH-Z DQ0-DQ6 Data In Status Data Valid Data HIGH-Z NOTE : DQ7=Vaild Data (The device has completed the internal operation). Figure 18: Data Polling During Internal Routine Operation Timings RY/BY Timing Diagram During Program/Erase Operation CE The rising edge of the last WE signal WE Entire progrming or erase operation RY/BY tBUSY Figure 19: RY/BY Timing Diagram During Program/Erase Operation Timings 4C Min 5 10 Max 90 65 25 16 Min 5 10 4D Max 90 70 30 16 Min 5 10 4E Max 90 80 30 16 - Parameter Program/Erase Valid to RY/BY Delay Chip Enable Access Time Output Enable Time CE & OE Disable Time Output Hold Time from Address, CE or OE OE Hold Time Symbol tBUSY tCE tOE tDF tOH tOEH2 Unit ns ns ns ns ns ns NOTE : 1) The device supports only 4E at VIO = 1.7~1.95V. - 48 - K8P2716UZC datasheet tAHT tAS Rev. 1.0 NOR FLASH MEMORY SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation Address* tAA CE tOEH2 WE tASO tOEPH OE tDH DQ6/DQ2 Data In Status Data tOE tAHT tCEPH Status Data Status Data Array Data Out RY/BY NOTE : A = Valid Address ; Not required for DQ6. The switching waveform shows first two status cycle after command sequence, last status read cycle, and array data read cycle CE does not need to go high between status bit reads. Enter Embedded Erasing Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete WE DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE NOTE : DQ2 is read from the erase-suspended block. Figure 20: Toggle Bit During Internal Routine Operation Timings - 49 - K8P2716UZC SWITCHING WAVEFORMS RESET Timing Diagram datasheet tRH Rev. 1.0 NOR FLASH MEMORY CE or OE RESET tRP Power-up and RESET Timing Diagram tRSTS RESET Vcc Vccmin Address DATA tAA Figure 21: Power-up and RESET Timing Diagram Parameter RESET Pulse Width RESET High Time Before Read RESET Low Set-up Time Symbol tRP tRH tRSTS All Speed Min 30 200 250 Max - Unit s ns s - 50 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program) CE WE Address PA DQ0-DQ15 Don't Care A0h Don't Care PD Don't Care OE 1us VHH tVPS WP/ACC VIL or VIH tVHH Unlock Bypass Block Erase Operations(Accelerated Program) CE WE Address BA 555h for chip erase 10h for chip erase 30h Don't Care DQ0-DQ15 Don't Care 80h Don't Care OE 1us VHH tVPS WP/ACC VIL or VIH tVHH NOTE : 1) VHH can be left high for subsequent programming pulses. 2) Use setup and hold times from conventional program operations. 3) Unlock Bypass Program/Erase commands can be used when the VHH is applied to WP/ACC Figure 22: Unlock Bypass Operation Timings - 51 - K8P2716UZC [Table 14] Address Table (Continued) Block BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 NOR FLASH MEMORY (x16) Address Range 7F0000h-7FFFFFh 7E0000h-7EFFFFh 7D0000h-7DFFFFh 7C0000h-7CFFFFh 7B0000h-7BFFFFh 7A0000h-7AFFFFh 790000h-79FFFFh 780000h-78FFFFh 770000h-77FFFFh 760000h-76FFFFh 750000h-75FFFFh 740000h-74FFFFh 730000h-73FFFFh 720000h-72FFFFh 710000h-71FFFFh 700000h-70FFFFh 6F0000h-6FFFFFh 6E0000h-6EFFFFh 6D0000h-6DFFFFh 6C0000h-6CFFFFh 6B0000h-6BFFFFh 6A0000h-6AFFFFh 690000h-69FFFFh 680000h-68FFFFh 670000h-67FFFFh 660000h-66FFFFh 650000h-65FFFFh 640000h-64FFFFh 630000h-63FFFFh 620000h-62FFFFh 610000h-61FFFFh 600000h-60FFFFh 5F0000h-5FFFFFh 5E0000h-5EFFFFh 5D0000h-5DFFFFh 5C0000h-5CFFFFh 5B0000h-5BFFFFh 5A0000h-5AFFFFh 590000h-59FFFFh 580000h-58FFFFh 570000h-57FFFFh 560000h-56FFFFh 550000h-55FFFFh 540000h-54FFFFh 530000h-53FFFFh 520000h-52FFFFh 510000h-51FFFFh - 52 - K8P2716UZC datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 NOR FLASH MEMORY (x16) Address Range 500000h-50FFFFh 4F0000h-4FFFFFh 4E0000h-4EFFFFh 4D0000h-4DFFFFh 4C0000h-4CFFFFh 4B0000h-4BFFFFh 4A0000h-4AFFFFh 490000h-49FFFFh 480000h-48FFFFh 470000h-47FFFFh 460000h-46FFFFh 450000h-45FFFFh 440000h-44FFFFh 430000h-43FFFFh 420000h-42FFFFh 410000h-41FFFFh 400000h-40FFFFh 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh Block BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 - 53 - K8P2716UZC datasheet Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords Rev. 1.0 NOR FLASH MEMORY (x16) Address Range 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh Block BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 - 54 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 22.0 PACKAGE DIMENSIONS 22.1 56-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE 56 - TSOP 18.400.10 Unit :mm #56 +0.07 -0.03 0.20 0.50TYP #28 #29 0.16 -0.01 +0.03 14.000.10 1.000.05 1.20 MAX 0.10 MAX 0.43750.05 0.43750.05 +0.075 -0.035 0.05 MIN 0.25 TYP 0.125 0~8 (19.00) 20.000.20 (0.50) 0.45~0.75 - 55 - K8P2716UZC datasheet Rev. 1.0 NOR FLASH MEMORY 22.2 64-Ball Fine Ball Grid Array Package (measured in millimeters) PACKAGE DIMENSIONS Top View Bottom View 11.00 0.10 1.00 x 7=7.00 1.00 A #A1 INDEX MARK 11.00 0.10 (Datum A) 8 7 6 5 4 3 2 1 B #A1 A (Datum B) 0.10 13.00 D F 0.50 E 3.50 G H 0.50 64- 0.60Solder Ball (POST REFLOW 0.62 0.05) 0.2 M A B 3.50 Side View 0.05 0.10 MAX 13.00 - 56 - 1.20 0.10 0.50 1.00x7= 7.00 13.00 0.10 C 1.00 B |
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